The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. For example, the invention is a technology applicable to a power transistor.
In some semiconductor device, a plurality of transistors are provided on a semiconductor substrate. In such a case, the transistors may be electrically isolated from one another using shallow trench isolation (STI).
Japanese Unexamined Patent Application Publication No. 2005-19703 (JP-A-2005-19703) describes an exemplary STI. In JP-A-2005-19703, first, a recess is formed on a surface of a silicon substrate. Subsequently, the recess is filled with an insulating film. Subsequently, the surface of the silicon substrate is etched. This allows the top of the insulating film to be located above the surface of the silicon substrate. Subsequently, an oxide film is formed on the surface of the silicon substrate by thermal oxidation. Subsequently, the oxide film is removed. Subsequently, a gate insulating film is formed on the surface of the silicon substrate by thermal oxidation. JP-A-2005-19703 describes that oxygen concentration is higher in the vicinity of the insulating film (recess) than in another region. JP-A-2005-19703 further describes that the gate insulating film has a larger thickness in the vicinity of the recess than in another region.